In modern semiconductor memories, the desire to lower power consumption has resulted in a decrease in the magnitude of a supply voltage VCC which provides power to the memories. Electronic systems typically benefit from lower power consumption, particularly portable systems which are battery powered. When the supply voltage VCC decreases, reference voltage circuitry in the memory that develops reference voltages which are a function of the supply voltage accordingly develop reference voltages having different values. For example, in many semiconductor memories digit lines are biased and equilibrated to a voltage equal to the supply voltage VCC divided by two. In this situation, a change in the supply voltage from 5 volts to 3.3 volts results in the reference voltage changing from 2.5 volts to 1.65 volts. Such a decrease in the reference voltage may affect the circuitry in the memory during operation.
One type of circuit that may be affected by a decrease in the bias voltage is a sense amplifier circuit. In a typical dynamic random access memory (“DRAM”), a sense amplifier circuit senses data stored in a memory cell by sensing a voltage differential between a pair of complementary digit lines associated with the memory cell, as known in the art. The sense amplifier circuit senses the voltage differential and drives the digit line at the higher voltage to approximately the supply voltage VCC and the digit line at the lower voltage to approximately zero volts. Typically, the sense amplifier circuit includes NMOS and PMOS transistors coupled between the digit lines. When the supply voltage VCC decreases, the threshold voltages VT of these transistors may prevent the sense amplifier circuit from driving the digit lines to the desired voltages as will be explained in more detail below.
FIG. 1 is a block diagram and simplified schematic of a conventional sense amplifier 12 having an open digit line configuration. The sense amplifier 12 senses data stored in memory cells (not shown) of cell arrays 2A, 2B that are coupled to complementary digit lines D, D_, respectively. As known, the cell arrays 2A, 2B typically include several digit lines D, D_ with each pair of digit line coupled to a respective sense amplifier. FIG. 1 illustrates only one of the sense amplifiers in order to simplify the following description. Binary data are stored in the memory cells utilizing a respective storage capacitor. The capacitor can be charged or can be left uncharged to store two types of data. When accessing a particular memory cell, the respective storage capacitor is coupled to a corresponding digit line. Prior to coupling the memory cell to the digit line, the digit line and a complementary digit line, both of which are coupled to a corresponding sense amplifier, are precharged to a voltage, typically VCC/2. In response to coupling the memory cell to the digit line, the stored charge or lack of charge causes a change in the voltage of digit line, which is detected by the sense amplifier coupled to the digit line. Based on the differential voltage between the digit line to which the memory cell is coupled and the complementary digit line, the sense amplifier amplifies and latches the data. The sense amplifier 12 includes PMOS transistors 20, 22 and NMOS transistors 24, 26 which are cross coupled to form PMOS and NMOS latches. The digit line D is coupled to a sense node 28 through an isolation transistor 6A and the digit line D_ is coupled to a sense node 30 through an isolation transistor 6B. An isolation switch driver circuit 10 provides ISOA, ISOB signals that control the isolation transistors 6A, 6B, respectively.
Operation of the sense amplifier will be described with reference to the timing diagram of FIG. 2. In the following example, it is assumed that the memory cell to be accessed is storing charge and is located in cell array 2A. Prior to time T0, a precharge circuit (not shown) sets the voltage of the digit lines D, D_ to VCC/2. At time T0, the ISOA, ISOB signals are driven to a pumped supply voltage VCCP that is greater than the VCC voltage. The ISOA, ISOB signals switch ON isolation transistors 6A, 6B to couple the digit lines D, D_ to the respective sense nodes 28, 30. At time T1, a word line (not shown) becomes active to couple the memory cell to the corresponding digit line D. As a result, the voltage of the digit line D is slightly increased. At a time T2, ACT and RNL_ signals become active, providing VCC to the sources of the PMOS transistors 20, 22 and ground to the sources of the NMOS transistors 24, 26. In response to the ACT and RNL_ signals, the sense amplifier 12 is activated and drives the digit line D to VCC and drives the digit line D_ to ground. In this state, the sense amplifier 12 has sensed and latched data.
As previously discussed, operation of conventional sense amplifiers can be affected by decreased VCC voltage. One effect is that the lower VCC/2 voltage to which the digit lines D, D_ are precharged approaches the VT of the NMOS transistors 24, 26. Consequently, when the ACT and RNL_ signals become active, the sensing operation can take longer because the NMOS transistors 24, 26 do not switch ON as quickly, waiting for the positive feedback of the PMOS latch to provide sufficient voltage to fully switch ON the NMOS transistors 24, 26. The NMOS transistors 24, 26 can be designed to have lower VTs to accommodate a lower VCC voltage. However, lowering the VT also reduces the resistance of the sense amplifier 12 to erroneous latching due to electrical noise which may be coupled through the digit lines D, D_ to the sense amplifier 12.
Therefore, there is a need for a sense amplifier and/or sensing scheme that can be used to quickly and reliably sense data stored in memory cells in a semiconductor memory having reduced supply voltage.